Modularize

1 files changed, 119 insertions, 0 deletions

diff --git a/src/bsp/drivers/uart/mod.rs b/src/bsp/drivers/uart/mod.rs
new file mode 100644
index 0000000..ad11e12
--- /dev/null
+++ b/src/bsp/drivers/uart/mod.rs
@@ -0,0 +1,119 @@
+/// # UART Registers
+pub mod UART {
+    /// # Flag Register
+    pub mod FR {
+        pub mod BUSY {
+            const MASK: u32 = 1 << 3;
+            pub fn is_set() -> bool {
+                super::read() & MASK != 0
+            }
+
+            pub fn is_clear() -> bool {
+                !is_set()
+            }
+        }
+        pub mod TXFF {
+            const MASK: u32 = 1 << 5;
+            pub fn is_set() -> bool {
+                super::read() & MASK != 0
+            }
+
+            pub fn is_clear() -> bool {
+                !is_set()
+            }
+        }
+        const ADDR: u32 = 0x3F201018;
+        //pub const TXFF: u32 = 1 << 5;
+        pub fn read() -> u32 {
+            use crate::cpu::load32;
+            load32(ADDR)
+        }
+    }
+    /// # Data Register
+    pub mod DR {
+        const ADDR: u32 = 0x3F201000;
+        pub fn set(c: char) {
+            use crate::cpu::store32;
+            store32(ADDR, c as u32);
+        }
+    }
+    /// # Control Register
+    pub mod CR {
+        const ADDR: u32 = 0x3F201030;
+        const UART_ENABLE: u32 = 1 << 0;
+        const TX_ENABLE: u32 = 1 << 8;
+        const RX_ENABLE: u32 = 1 << 9;
+        pub fn set(v: u32) {
+            use crate::cpu::store32;
+            store32(ADDR, v);
+        }
+        pub fn off() {
+            set(0);
+        }
+        pub fn all_on() {
+            set(UART_ENABLE + TX_ENABLE + RX_ENABLE)
+        }
+    }
+    /// # Integer Baud Rate
+    pub mod IBRD {
+        const ADDR: u32 = 0x3F201024;
+        pub fn set(v: u32) {
+            use crate::cpu::store32;
+            store32(ADDR, v);
+        }
+    }
+    /// # Fractional Baud Rate
+    pub mod FBRD {
+        const ADDR: u32 = 0x3F201028;
+        pub fn set(v: u32) {
+            use crate::cpu::store32;
+            store32(ADDR, v);
+        }
+    }
+    /// # Interrupt Control Register
+    pub mod ICR {
+        const ADDR: u32 = 0x3F201044;
+        pub fn set(v: u32) {
+            use crate::cpu::store32;
+            store32(ADDR, v);
+        }
+        pub fn clear() {
+            set(0x7FF);
+        }
+    }
+    /// # Line Control Register
+    pub mod LCRH {
+        const ADDR: u32 = 0x3F20102C;
+        const FIFO_ENABLE: u32 = 1 << 4;
+        const FIVE_BIT: u32 = 0b00 << 5;
+        const SIX_BIT: u32 = 0b01 << 5;
+        const SEVEN_BIT: u32 = 0b10 << 5;
+        const EIGHT_BIT: u32 = 0b11 << 5;
+        pub fn set(v: u32) {
+            use crate::cpu::store32;
+            store32(ADDR, v);
+        }
+        pub fn enable8() {
+            set(FIFO_ENABLE + EIGHT_BIT);
+        }
+    }
+    /// # Interrupt Mask Set/ Clear Register
+    pub mod IMSC {
+        const ADDR: u32 = 0x3F201038;
+        const MASK: u32 =
+            (1 << 1) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10);
+        pub fn set(v: u32) {
+            use crate::cpu::store32;
+            store32(ADDR, v);
+        }
+        pub fn mask() {
+            set(MASK);
+        }
+    }
+}
+
+mod console;
+pub use console::*;
+
+/// # Public reference to console.
+pub static UART_WRITER: Uart = Uart::new();