diff options
| author | Christian Cunningham <cc@localhost> | 2022-02-09 22:26:43 -0700 |
|---|---|---|
| committer | Christian Cunningham <cc@localhost> | 2022-02-09 22:26:43 -0700 |
| commit | cd32aaf0510088768e4dd20ea22f92cad9f4367d (patch) | |
| tree | f1f3101d4bbfc2fa8906d87c928421a1f32a0103 /src | |
| parent | a3ba24739c2309df5e39ad8bdcfca171b1eec5a3 (diff) | |
Add interrupt to all cores
Diffstat (limited to 'src')
| -rw-r--r-- | src/boot.S | 10 | ||||
| -rw-r--r-- | src/sys/core.c | 2 | ||||
| -rw-r--r-- | src/sys/kernel.S | 2 |
3 files changed, 10 insertions, 4 deletions
@@ -20,7 +20,6 @@ reset: // set vector address. ldr r0, =vector mcr p15, 0, r0, c12, c0, 0 - cps #0x12 // Setup sp in IRQ mode. ldr sp, =core0_irq_stack cps #0x11 // Setup sp in FIQ mode. @@ -66,6 +65,9 @@ reset: blx r3 core1run: + // set vector address. + ldr r0, =vector + mcr p15, 0, r0, c12, c0, 0 cps #0x12 // Setup sp in IRQ mode. ldr sp, =core1_irq_stack cps #0x11 // Setup sp in FIQ mode. @@ -80,6 +82,9 @@ core1run: ldr sp, =core1_svc_stack b io_halt core2run: + // set vector address. + ldr r0, =vector + mcr p15, 0, r0, c12, c0, 0 cps #0x12 // Setup sp in IRQ mode. ldr sp, =core2_irq_stack cps #0x11 // Setup sp in FIQ mode. @@ -94,6 +99,9 @@ core2run: ldr sp, =core2_svc_stack b io_halt core3run: + // set vector address. + ldr r0, =vector + mcr p15, 0, r0, c12, c0, 0 cps #0x12 // Setup sp in IRQ mode. ldr sp, =core3_irq_stack cps #0x11 // Setup sp in FIQ mode. diff --git a/src/sys/core.c b/src/sys/core.c index 65ee526..e987e8c 100644 --- a/src/sys/core.c +++ b/src/sys/core.c @@ -40,8 +40,6 @@ void sysinit(void) cntfrq = read_cntfrq(); // Clear cntv interrupt and set next 1 second timer write_cntv_tval(cntfrq); - //// Route timer to core0 irq - //routing_core0cntv_to_core0irq(); // Route timer to core0 fiq routing_core0cntv_to_core0fiq(); // Enable timer diff --git a/src/sys/kernel.S b/src/sys/kernel.S index 119a00d..90e1c4f 100644 --- a/src/sys/kernel.S +++ b/src/sys/kernel.S @@ -2,13 +2,13 @@ .globl kernel_main kernel_main: - bl sysinit ///https://wiki.osdev.org/ARM_Paging // Query the ID_MMFR0 register mrc p15, 0, r2, c0, c1, 4 mov r0, #0 mov r1, #7 bl draw_hex32 + bl sysinit // Intentional undefined instruction // .word 0xf7f0a000 cpsie aif, #0x10 |