From cd32aaf0510088768e4dd20ea22f92cad9f4367d Mon Sep 17 00:00:00 2001
From: Christian Cunningham <cc@localhost>
Date: Wed, 9 Feb 2022 22:26:43 -0700
Subject: Add interrupt to all cores

---
 src/boot.S       | 10 +++++++++-
 src/sys/core.c   |  2 --
 src/sys/kernel.S |  2 +-
 3 files changed, 10 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/boot.S b/src/boot.S
index 9259874..e4da373 100644
--- a/src/boot.S
+++ b/src/boot.S
@@ -20,7 +20,6 @@ reset:
 	// set vector address.
 	ldr r0, =vector
 	mcr p15, 0, r0, c12, c0, 0
-
 	cps #0x12 // Setup sp in IRQ mode.
 	ldr sp, =core0_irq_stack
 	cps #0x11 // Setup sp in FIQ mode.
@@ -66,6 +65,9 @@ reset:
 	blx r3
 
 core1run:
+	// set vector address.
+	ldr r0, =vector
+	mcr p15, 0, r0, c12, c0, 0
 	cps #0x12 // Setup sp in IRQ mode.
 	ldr sp, =core1_irq_stack
 	cps #0x11 // Setup sp in FIQ mode.
@@ -80,6 +82,9 @@ core1run:
 	ldr sp, =core1_svc_stack
 	b io_halt
 core2run:
+	// set vector address.
+	ldr r0, =vector
+	mcr p15, 0, r0, c12, c0, 0
 	cps #0x12 // Setup sp in IRQ mode.
 	ldr sp, =core2_irq_stack
 	cps #0x11 // Setup sp in FIQ mode.
@@ -94,6 +99,9 @@ core2run:
 	ldr sp, =core2_svc_stack
 	b io_halt
 core3run:
+	// set vector address.
+	ldr r0, =vector
+	mcr p15, 0, r0, c12, c0, 0
 	cps #0x12 // Setup sp in IRQ mode.
 	ldr sp, =core3_irq_stack
 	cps #0x11 // Setup sp in FIQ mode.
diff --git a/src/sys/core.c b/src/sys/core.c
index 65ee526..e987e8c 100644
--- a/src/sys/core.c
+++ b/src/sys/core.c
@@ -40,8 +40,6 @@ void sysinit(void)
 	cntfrq = read_cntfrq();
 	// Clear cntv interrupt and set next 1 second timer
 	write_cntv_tval(cntfrq);
-	//// Route timer to core0 irq
-	//routing_core0cntv_to_core0irq();
 	// Route timer to core0 fiq
 	routing_core0cntv_to_core0fiq();
 	// Enable timer
diff --git a/src/sys/kernel.S b/src/sys/kernel.S
index 119a00d..90e1c4f 100644
--- a/src/sys/kernel.S
+++ b/src/sys/kernel.S
@@ -2,13 +2,13 @@
 
 .globl kernel_main
 kernel_main:
-	bl sysinit
 	///https://wiki.osdev.org/ARM_Paging
 	// Query the ID_MMFR0 register
 	mrc p15, 0, r2, c0, c1, 4
 	mov r0, #0
 	mov r1, #7
 	bl draw_hex32
+	bl sysinit
 	// Intentional undefined instruction
 	// .word 0xf7f0a000
 	cpsie aif, #0x10
-- 
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